{"id":1342,"date":"2026-08-07T05:29:05","date_gmt":"2026-08-07T05:29:05","guid":{"rendered":"https:\/\/proactivepcb.com\/articles\/uncategorized\/hdi-pcb-signal-integrity-design\/"},"modified":"2026-08-07T05:29:05","modified_gmt":"2026-08-07T05:29:05","slug":"hdi-pcb-signal-integrity-design","status":"publish","type":"post","link":"https:\/\/proactivepcb.com\/articles\/pcb-design-dfm\/hdi-pcb-signal-integrity-design\/","title":{"rendered":"HDI PCB Signal Integrity Design: Best Practices"},"content":{"rendered":"<h2 id=\"key-takeaways\">Key Takeaways<\/h2>\n<ul>\n<li>HDI PCB signal integrity depends on early stack-up planning, symmetric copper balance and continuous reference planes that support accurate simulation and reliable manufacturing.<\/li>\n<li>Microvia aspect ratios must stay below IPC-2226 limits, staggered configurations support high-reliability programs and via-in-pad structures need correct fill and capping to prevent solder defects.<\/li>\n<li>Controlled-impedance routing requires field-solver-validated geometries, dielectric materials chosen by loss class at operating frequency and strict use of the 3W spacing rule for crosstalk control.<\/li>\n<li>Return-path continuity relies on deliberate ground stitching vias at every layer transition, symmetric patterns for differential pairs and strict avoidance of routing over plane splits.<\/li>\n<li>Pro-Active Engineering integrates DFM from day one and builds production-ready prototypes using the same processes as volume manufacturing; <a href=\"https:\/\/proactivepcb.com\/quote\/\" target=\"_blank\" rel=\"noindex nofollow\">embed these 12 rules into your next HDI program<\/a> with Pro-Active\u2019s engineering team.<\/li>\n<\/ul>\n<h2>Stack-Up Planning That Protects Signal Integrity<\/h2>\n<p>Early stack-up decisions define what remains manufacturable in the finished HDI board and rarely change after routing without a complete re-spin. The most critical of these early decisions is symmetrical construction, which mirrors copper weight and layer order around the board mid-plane and defends against warpage during lamination and reflow. This symmetry minimizes warpage by balancing copper distribution and dielectric thickness on both sides of the board.<\/p>\n<p>Reference-plane adjacency is equally critical for signal integrity. Placing sensitive high-speed traces between two ground planes on inner layers creates strong return paths and reduces EMI for signals such as PCIe or DDR. Power and ground plane pairs placed close together increase plane capacitance and lower PDN impedance, which reduces the need for additional decoupling components.<\/p>\n<p>Beyond plane placement, copper balance across layers must stay within a tight window to preserve registration and yield. <a href=\"https:\/\/dxcircuit.com\/blog-hdi-pcb-design-guide.html\" target=\"_blank\" rel=\"noindex nofollow\">Asymmetric copper distribution in thin sequentially laminated boards induces warpage that degrades registration tolerance and yield during multiple lamination cycles.<\/a><\/p>\n<p>Pro-Active Engineering integrates stack-up review into the design phase, not after routing. DFM built in from day one resolves fabrication constraints before they become respins. <a href=\"https:\/\/proactivepcb.com\/quote\/\" target=\"_blank\" rel=\"noindex nofollow\">Discuss stack-up planning for your current program<\/a> with Pro-Active\u2019s engineering team.<\/p>\n<h2>Microvia Choices That Support Reliability<\/h2>\n<p>Microvia aspect ratio discipline represents the most consequential DFM decision in HDI design. <a href=\"https:\/\/rapidcircuitry.com\/blogs\/hdi-pcb-design-guide-2026-microvias-stackups--dfm\" target=\"_blank\" rel=\"noindex nofollow\">Microvias with aspect ratio exceeding the IPC-2226 maximum produce plating voids and weak interface bonds that pass electrical test but fail under thermal cycling.<\/a> Because fabricator dielectric thickness variation can push a nominal design over that limit, designing with margin below the maximum is standard practice for high-reliability programs.<\/p>\n<p>The staggered versus stacked trade-off carries direct reliability consequences. Staggered multi-level microvias distribute thermo-mechanical stress and can achieve better reliability than copper-filled stacked configurations under thermal cycling. For aerospace and defense programs, staggered configurations serve as the preferred default. Stacked microvias remain appropriate where routing density demands them, but they require copper filling, planarization and stricter cross-section inspection per IPC-6012 Class 3.<\/p>\n<p>Whether staggered or stacked, microvias used in via-in-pad configurations introduce an additional layer of process control. Via-in-pad implementations require resin plug filling, planarization and copper capping. <a href=\"https:\/\/hdicircuitboard.com\/via-in-pad-hdi-pcb-guide\" target=\"_blank\" rel=\"noindex nofollow\">VIPPO with nonconductive epoxy, conductive or copper fill plus copper capping is required for solderable pads to prevent solder wicking, BGA voiding and pad dimpling.<\/a> Surface dimple after planarization must stay tightly controlled; <a href=\"https:\/\/hdicircuitboard.com\/hdi-pcb-design-guidelines-for-engineers\" target=\"_blank\" rel=\"noindex nofollow\">dimple variation was identified as a root cause of BGA solder defects in a documented fine-pitch prototype.<\/a><\/p>\n<h2>Controlled-Impedance Routing in HDI Stack-Ups<\/h2>\n<p>Controlled impedance in HDI depends on trace geometry, dielectric properties and transition continuity working together. Controlled-impedance traces in HDI stack-ups require validation with a field solver because trace impedance changes when prepreg thickness or the reference plane changes.<\/p>\n<p>Dielectric control functions as a fabrication variable, not only a design variable. <a href=\"https:\/\/hdicircuitboard.com\/dfm-tips-for-hdi-circuit-board-high-yield-manufacturing-guidelines\" target=\"_blank\" rel=\"noindex nofollow\">HDI designs must maintain dielectric tolerance within tight limits to achieve controlled impedance for standard single-ended and differential targets.<\/a> Achieving that tolerance in production requires a complete controlled-impedance specification that includes layer number, trace width, target impedance, tolerance and reference plane layer names. <a href=\"https:\/\/hilelectronic.com\/pcb-design-for-manufacturing\" target=\"_blank\" rel=\"noindex nofollow\">Omitting any element forces the fabricator to use a default stack-up and produces lot-to-lot impedance variation.<\/a><\/p>\n<p>Via transitions introduce discontinuities that simulation must capture. <a href=\"https:\/\/queenems.com\/blog\/how-to-design-an-hdi-pcb-for-pcie-5-0-ddr5\" target=\"_blank\" rel=\"noindex nofollow\">HDI microvia transitions deliver measurably better eye opening than back-drilled PTH vias at high data rates by eliminating via stubs.<\/a> Back-drilling, where through-hole vias are used, removes stub length and serves as a standard technique for managing via resonance on high-speed channels.<\/p>\n<h2>Crosstalk Control in Dense HDI Layouts<\/h2>\n<p>Crosstalk in dense HDI layouts is controlled through spacing discipline, reference plane continuity and routing layer selection. <a href=\"https:\/\/hdicircuitboard.com\/dfm-tips-for-hdi-circuit-board-high-yield-manufacturing-guidelines\" target=\"_blank\" rel=\"noindex nofollow\">Implementing the 3W rule, with trace center-to-center spacing at or above three times trace width, reduces crosstalk meaningfully for high-speed paths above 1 Gbps.<\/a><\/p>\n<p>For differential pairs, inter-pair spacing must exceed intra-pair spacing by a clear margin. <a href=\"https:\/\/hdicircuitboard.com\/differential-pair-routing-rules-for-high-speed-interfaces\" target=\"_blank\" rel=\"noindex nofollow\">In a documented HDI stack-up for PCIe signals, increasing inter-pair spacing substantially reduced crosstalk while symmetric via placement and serpentine tuning lowered skew and raised manufacturing yield.<\/a><\/p>\n<p>Guard traces act as a supplemental tool but require stitching vias at regular intervals. <a href=\"https:\/\/blog.lamsimenterprises.com\/2013\/04\/12\/are-guard-traces-worth-it\/\" target=\"_blank\" rel=\"noindex nofollow\">Guard traces are typically stitched to ground with vias spaced at one-tenth of the highest-frequency wavelength to prevent them from acting as floating antennas.<\/a> For nets where even grounded guard traces do not provide sufficient isolation, stripline routing on inner layers between two reference planes provides inherent shielding and is preferred over microstrip for the most sensitive high-speed nets.<\/p>\n<h2>Low-Loss Material Choices for HDI<\/h2>\n<p>Material selection for HDI signal integrity starts with dissipation factor at the actual operating frequency. Df is the primary driver of dielectric attenuation and insertion loss at a given frequency. Dielectric constant primarily affects impedance and propagation velocity.<\/p>\n<p>Standard FR-4 suits lower-speed designs but becomes a limiting factor as data rates increase. <a href=\"https:\/\/hdicircuitboard.com\/high-speed-pcb-design-for-pcie-5-0-6-0\" target=\"_blank\" rel=\"noindex nofollow\">Standard FR-4 is limited to lower frequencies, which makes it unsuitable for high-speed serial link designs operating at multi-gigabit rates.<\/a> At those higher data rates, low-loss and very-low-loss laminates extend channel reach and improve eye diagrams. For the most demanding interfaces operating at the highest frequencies, ultra-low-loss materials are required.<\/p>\n<p>Hybrid stack-ups provide a practical cost-management strategy. <a href=\"https:\/\/rfessentials.com\/rf-knowledge-base\/how-do-i-select-the-right-pcb-material-for-a-25-gbps-or-56-gbps-serial-link\" target=\"_blank\" rel=\"noindex nofollow\">Hybrid stack-ups using low-loss laminate on signal layers and standard material on power and ground layers are common, provided differing Dk values are accounted for in impedance calculations and lamination compatibility is verified with the fabricator.<\/a><\/p>\n<p>Copper foil roughness compounds dielectric loss at high frequencies. At high frequencies, skin-effect losses caused by standard electrodeposited copper roughness can compound dielectric losses, so specifying low-roughness copper foils on low-Df laminates preserves the benefits of ultra-low-loss materials.<\/p>\n<p>Beyond the copper itself, the fiber-weave effect is a separate concern for phase-matched signaling. Fiber weave effect in standard glass styles creates local Dk variation that induces skew and mode conversion; mitigation uses spread-glass weaves or routing traces at an angle to the weave direction.<\/p>\n<h2>Return-Path and Stitching-Via Practices<\/h2>\n<p>Return-path management in HDI requires deliberate ground stitching at every signal layer transition. Microvias connect only adjacent layers, unlike through-hole vias that automatically maintain continuity across all planes, so effective return path management requires deliberate ground stitching at every signal layer transition.<\/p>\n<p>Proximity of the stitching via to the signal via sets loop inductance. <a href=\"https:\/\/ugpcb.com\/news\/pcb-tech\/electronic-design\/high-speed-pcb-loop-control\" target=\"_blank\" rel=\"noindex nofollow\">For single-ended signals, one adjacent ground via placed close to the signal via is recommended; for differential pairs, two ground vias near each differential via pair reduce loop area and preserve balance.<\/a><\/p>\n<p>Symmetric stitching patterns are mandatory for differential pairs that cross layers. For differential pairs in HDI, symmetric via patterns such as GSG or GSSG should be used during layer transitions so the return path remains balanced and differential impedance is preserved.<\/p>\n<p>Distributed plane-to-plane stitching via arrays address board-level PDN integrity. Distributed stitching via arrays connect plane pairs throughout the board, raise resonant frequencies and reduce Q-factor by acting as a shorting grid. Even with distributed stitching in place, routing high-speed signals over plane splits must be avoided. <a href=\"https:\/\/ugpcb.com\/news\/pcb-tech\/electronic-design\/high-speed-pcb-loop-control\" target=\"_blank\" rel=\"noindex nofollow\">When a high-speed differential signal crosses a ground plane split, return path inductance increases substantially and radiated EMI peaks rise.<\/a><\/p>\n<h2>Recommended SI\/PI Simulation Workflow<\/h2>\n<p>Simulation checkpoints must map to design stages so that findings drive decisions rather than confirm them after routing is complete. Stack-up validation should occur before layout begins, using 2D field solvers to confirm trace geometries meet impedance targets. During routing, incremental SI analysis validates critical net topologies as they reach completion. After layout, full-channel simulation including package models, vias and connectors confirms margin against specification limits.<\/p>\n<p>To confirm that fabrication matches simulation assumptions, <a href=\"https:\/\/rfessentials.com\/rf-knowledge-base\/how-do-i-select-the-right-pcb-material-for-a-25-gbps-or-56-gbps-serial-link\" target=\"_blank\" rel=\"noindex nofollow\">test coupons should be requested on the production panel and measured with a VNA using production-style launches; measured insertion loss versus frequency must agree with simulation within an acceptable tolerance for validation before volume production.<\/a><\/p>\n<h2>Manufacturing Risks That Affect Signal Integrity<\/h2>\n<p>The design rules outlined above, including stack-up symmetry, microvia aspect ratios, controlled impedance and return-path continuity, all depend on fabrication variables that must be constrained during the design phase. Several fabrication variables directly degrade signal integrity if not addressed before routing is complete.<\/p>\n<p><strong>Aspect-ratio limits.<\/strong> <a href=\"https:\/\/hilelectronic.com\/pcb-design-for-manufacturing\" target=\"_blank\" rel=\"noindex nofollow\">The aspect-ratio failures described earlier occur when plating chemistry cannot reach the barrel center, producing thin copper that cracks after thermal cycling.<\/a><\/p>\n<p><strong>Copper-fill considerations.<\/strong> As noted in the stack-up planning section, copper density must stay within a controlled range across layers to avoid warpage. <a href=\"https:\/\/dxcircuit.com\/blog-hdi-pcb-design-guide.html\" target=\"_blank\" rel=\"noindex nofollow\">This warpage degrades registration tolerance and yield during multiple lamination cycles and becomes a manufacturing risk when copper balance is not verified during design review.<\/a><\/p>\n<p><strong>Registration tolerances.<\/strong> <a href=\"https:\/\/hilelectronic.com\/pcb-design-for-manufacturing\" target=\"_blank\" rel=\"noindex nofollow\">Standard CNC drilling registration tolerance directly consumes annular ring; a minimal ring leaves little margin on inner layers and creates breakout risk in production.<\/a> Each sequential lamination cycle introduces additional dimensional drift. <a href=\"https:\/\/rapidcircuitry.com\/blogs\/hdi-pcb-design-guide-2026-microvias-stackups--dfm\" target=\"_blank\" rel=\"noindex nofollow\">Each additional microvia layer adds a sequential lamination press cycle that increases registration risk, lead time and cost multipliers versus conventional PCBs.<\/a><\/p>\n<p><strong>Sequential-lamination effects.<\/strong> This cumulative drift creates another opportunity for registration error with each build-up level, so removing an unnecessary build-up level can improve manufacturability and yield without changing product function.<\/p>\n<p><strong>Prototype-to-production transfer.<\/strong> Prototype and production HDI boards should use the same critical stack-up, via architecture and acceptance basis when the prototype is intended to validate production behavior; a simplified prototype may confirm circuit function but cannot validate a different interconnect structure for transfer success.<\/p>\n<p>Pro-Active Engineering\u2019s production-ready prototypes use the same processes as full-scale builds, so performance proven in development scales directly into manufacturing. <a href=\"https:\/\/proactivepcb.com\/quote\/\" target=\"_blank\" rel=\"noindex nofollow\">Start a program with DFM built in from day one<\/a>.<\/p>\n<h2>From Rules to Production: Pro-Active Engineering Workflow Checklist<\/h2>\n<p>The manufacturing risks outlined above, including aspect-ratio failures, copper imbalance, registration drift and prototype-to-production mismatches, are all prevented by embedding the 12 design rules into a single integrated engineering-to-production workflow rather than handing them off between separate vendors. The checklist below maps each rule to Pro-Active Engineering\u2019s process.<\/p>\n<ol>\n<li><strong>Stack-up locked before routing:<\/strong> Pro-Active\u2019s engineering team conducts stack-up review before layout begins and validates dielectric selection, copper balance and sequential lamination count with production constraints in view.<\/li>\n<li><strong>Symmetric, copper-balanced construction:<\/strong> DFM review confirms copper distribution across layers and flags asymmetry risks before the design reaches fabrication.<\/li>\n<li><strong>Reference planes adjacent to critical signal layers:<\/strong> Layer assignment is reviewed against the signal list during the design phase, not after routing.<\/li>\n<li><strong>Microvia aspect ratios within process-proven limits:<\/strong> Pro-Active\u2019s advanced interconnect capabilities include tight-tolerance microvia structures aligned with IPC-2226 and IPC-6012 Class 3 requirements for high-reliability programs.<\/li>\n<li><strong>Staggered microvias preferred:<\/strong> Via architecture decisions rely on reliability data and program requirements, and stacked configurations receive explicit qualification planning.<\/li>\n<li><strong>Via-in-pad filled and capped:<\/strong> Fill material, copper cap and dimple control are specified and verified as part of the production process, not as afterthoughts.<\/li>\n<li><strong>Dielectric material specified by loss class at operating frequency:<\/strong> Material selection is coordinated between engineering and manufacturing to confirm fabricator availability and lamination compatibility.<\/li>\n<li><strong>Field-solver-validated trace geometries:<\/strong> Controlled-impedance specifications include layer, trace width, target, tolerance and reference plane, complete enough to eliminate fabricator ambiguity.<\/li>\n<li><strong>3W spacing applied to high-speed nets:<\/strong> Crosstalk rules are enforced during layout review before prototype release.<\/li>\n<li><strong>Ground stitching vias at every layer transition:<\/strong> Return-path continuity is verified during design review using EDA tools before fabrication.<\/li>\n<li><strong>No high-speed routing over plane splits:<\/strong> Plane integrity is confirmed during DFM review as part of the standard pre-release checklist.<\/li>\n<li><strong>SI\/PI simulation checkpoints and test coupon validation:<\/strong> Simulation outputs are reviewed at each design stage, and test coupons on production panels confirm correlation before volume production.<\/li>\n<\/ol>\n<p>Pro-Active Engineering is an ITAR-registered, AS9100 and ISO 9001:2015 certified domestic manufacturer with Nadcap accreditation and JCP certification. All design, prototyping, assembly, testing and system integration occur under one roof in Sun Prairie, Wisconsin, with a single accountable team from concept through production. For aerospace, defense and medical programs that cannot accept late-stage signal integrity failures, that integration functions as a core risk-reduction strategy. <a href=\"https:\/\/proactivepcb.com\/quote\/\" target=\"_blank\" rel=\"noindex nofollow\">Connect with Pro-Active\u2019s engineering team<\/a> to start your next program.<\/p>\n<h2>Frequently Asked Questions<\/h2>\n<h3>What is the difference between staggered and stacked microvias, and which suits high-reliability HDI programs?<\/h3>\n<p>Staggered microvias offset horizontally between build-up layers so each via lands on a separate pad rather than directly on top of the via below. Stacked microvias align vertically, with each successive via drilled on top of the one beneath it after copper filling and planarization. Staggered configurations distribute thermo-mechanical stress across a wider area, which supports stronger reliability margins under thermal cycling. Stacked configurations save board area and can improve signal integrity for high-speed nets by shortening vertical transitions, but every interface in the stack acts as a stress concentrator. For aerospace, defense and medical programs qualified to IPC-6012 Class 3, staggered microvias serve as the preferred default, while stacked microvias are reserved for regions where routing density demands them and receive explicit qualification including cross-section inspection and additional thermal-cycle testing.<\/p>\n<h3>How does dielectric material selection affect signal integrity in HDI PCBs?<\/h3>\n<p>Dielectric material affects signal integrity through dissipation factor and dielectric constant. Df governs how much signal energy the dielectric absorbs and converts to heat, so lower Df supports lower insertion loss, better eye diagrams and longer usable channel reach at high data rates. Dk governs impedance and signal propagation velocity, and variation in Dk across a production run produces variation in trace impedance and propagation delay. Standard FR-4 suits lower-speed designs but becomes a limiting factor as data rates increase into multi-gigabit territory. Low-loss and very-low-loss laminates extend channel performance at higher data rates, and ultra-low-loss materials support the most demanding serial interfaces. Material must be specified at the actual operating frequency, not only at a nominal low-frequency datasheet value, because both Dk and Df depend on frequency. Hybrid stack-ups that use low-loss laminate on critical signal layers and standard material on power and ground layers provide a common cost-management strategy when lamination compatibility is confirmed with the fabricator.<\/p>\n<h3>Why do return-path discontinuities matter more in HDI designs than in conventional multilayer PCBs?<\/h3>\n<p>In conventional through-hole multilayer PCBs, a single via connects all layers simultaneously, so return current receives a direct path to the new reference plane at every layer transition. In HDI designs, microvias connect only adjacent layer pairs. When a signal transitions through multiple layers using stacked or staggered microvias, the return current must also transition through the same layer pairs using adjacent ground microvias. If those ground microvias are missing, partial or placed too far from the signal via, return current spreads laterally across the reference plane to find a path, which increases loop inductance, generates EMI and creates impedance discontinuities that degrade signal integrity. This problem intensifies in fine-pitch BGA escape regions where many transitions concentrate in a small area. The solution uses deliberate ground stitching via placement at every signal layer transition, symmetric patterns for differential pairs and distributed plane-to-plane stitching arrays across the board. These decisions must occur during layout and be verified with EDA tools before fabrication, because return-path discontinuities cannot be corrected after the board is built.<\/p>\n<h3>What DFM issues most often cause prototype-to-production transfer failures in HDI programs?<\/h3>\n<p>The most common causes of prototype-to-production transfer failure in HDI programs fall into several categories. First, stack-up changes between prototype and production mean a simplified prototype stack-up may reduce cost or lead time but only validates circuit function, not the interconnect structure used in production. Second, microvia aspect ratios that sit at or beyond process limits can pass initial electrical test but fail under thermal cycling in production environments. Third, via-in-pad structures without proper fill, cap and dimple control produce solder wicking voids under fine-pitch BGAs that appear only during assembly. Fourth, ambiguous or incomplete controlled-impedance specifications force fabricators to make assumptions that produce lot-to-lot variation. Fifth, copper imbalance and asymmetric stack-ups cause warpage that degrades registration tolerance across sequential lamination cycles. The most effective mitigation uses early DFM collaboration with the fabricator before routing is complete, the same stack-up and via architecture for both prototype and production builds and test coupons on production panels for electrical and cross-section validation.<\/p>\n<h3>How does Pro-Active Engineering support HDI PCB programs from design through production?<\/h3>\n<p>Pro-Active Engineering provides an integrated engineering-to-production workflow that covers PCB layout and design for manufacturability, rapid prototyping through the dedicated Speed Shop, PCB assembly and scalable manufacturing, advanced interconnect and packaging and full system integration under one roof. For HDI programs, this structure means stack-up review, microvia architecture decisions, material selection and controlled-impedance specifications are resolved during the design phase with production constraints already in view. Prototypes are built using the same processes as full-scale production builds, so performance validated at prototype transfers directly to volume manufacturing. Pro-Active holds ISO 9001:2015, AS9100, ITAR, JCP and Nadcap certifications, which support the documentation, traceability and compliance requirements of aerospace, defense and medical programs. Engineering and manufacturing operate within one workflow, which removes vendor fragmentation and communication gaps that often cause late-stage signal integrity failures and program delays.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>HDI PCB signal integrity starts with stack-up, microvias and impedance control. Pro-Active Engineering builds production-ready prototypes.<\/p>\n","protected":false},"author":68,"featured_media":1341,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"inline_featured_image":false,"footnotes":""},"categories":[8],"tags":[],"class_list":["post-1342","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-pcb-design-dfm"],"_links":{"self":[{"href":"https:\/\/proactivepcb.com\/articles\/wp-json\/wp\/v2\/posts\/1342","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/proactivepcb.com\/articles\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/proactivepcb.com\/articles\/wp-json\/wp\/v2\/types\/post"}],"replies":[{"embeddable":true,"href":"https:\/\/proactivepcb.com\/articles\/wp-json\/wp\/v2\/comments?post=1342"}],"version-history":[{"count":0,"href":"https:\/\/proactivepcb.com\/articles\/wp-json\/wp\/v2\/posts\/1342\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/proactivepcb.com\/articles\/wp-json\/wp\/v2\/media\/1341"}],"wp:attachment":[{"href":"https:\/\/proactivepcb.com\/articles\/wp-json\/wp\/v2\/media?parent=1342"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/proactivepcb.com\/articles\/wp-json\/wp\/v2\/categories?post=1342"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/proactivepcb.com\/articles\/wp-json\/wp\/v2\/tags?post=1342"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}