{"id":243,"date":"2026-03-26T05:10:49","date_gmt":"2026-03-26T05:10:49","guid":{"rendered":"https:\/\/blog.proactivepcb.com\/uncategorized\/best-practices-fc-pcba-ict\/"},"modified":"2026-08-17T05:12:31","modified_gmt":"2026-08-17T05:12:31","slug":"best-practices-fc-pcba-ict","status":"publish","type":"post","link":"https:\/\/proactivepcb.com\/articles\/pcb-testing-validation\/best-practices-fc-pcba-ict\/","title":{"rendered":"Best Practices for FC PCBA In-Circuit Testing Coverage"},"content":{"rendered":"<p><em>Last updated: August 14, 2026<\/em><\/p>\n<h2 id=\"key-takeaways\">Key Takeaways for FC PCBA ICT Coverage<\/h2>\n<ul>\n<li>ICT coverage is the percentage of electrical nets on a PCBA that an in-circuit test program can structurally verify through direct probe contact, boundary scan, vectorless techniques or supplemental inspection methods.<\/li>\n<li>Best practices for FC PCBA in-circuit testing require documented coverage goals with critical nets such as power rails, clock lines, reset signals and safety-critical paths assigned a 100% access requirement regardless of package density.<\/li>\n<li>High ICT coverage on flip-chip and BGA assemblies comes from mapping netlists to test-point feasibility, applying DFT-compliant pad sizing and spacing rules and integrating boundary scan and AXI supplementation for inaccessible nets.<\/li>\n<li>A compliant ICT coverage report separates results by method, states the numerator and denominator, lists excluded nets with justification and includes board revision and test program version for traceability in regulated programs.<\/li>\n<li>Pro-Active Engineering delivers integrated ICT fixture design, boundary-scan strategy and coverage reporting under one ISO 9001:2015, AS9100 and Nadcap-accredited quality system <a href=\"https:\/\/proactivepcb.com\/quote\/\" target=\"_blank\" rel=\"noindex nofollow\">to support FC PCBA programs<\/a>.<\/li>\n<\/ul>\n<h2>Step 1: Set Coverage Targets and Apply the Critical-Net 100% Rule<\/h2>\n<p>Regulated programs in defense, aerospace and medical device manufacturing require documented measurable coverage targets rather than informal estimates. Low coverage on a PCBA often correlates with defect escapes during ICT and can reveal DFT gaps that were not addressed during layout.<\/p>\n<figure style=\"text-align: center\"><img decoding=\"async\" src=\"https:\/\/cdn.aigrowthmarketer.co\/1785164810004-543392f76f6d.webp\" alt=\"An engineer in a lab coat holds a clipboard beside a large red PCB panel.\" style=\"max-height: 500px\" loading=\"lazy\"><figcaption><em>Engineering-forward, hands-on accountability. Design engineers review boards and panels against spec \u2014 the DFM-from-day-one discipline that turns prototypes into production seamlessly.<\/em><\/figcaption><\/figure>\n<p>Best practices for FC PCBA in-circuit testing emphasize high overall net coverage. Critical nets such as power rails, clock lines, reset signals and safety-critical paths follow a 100% access requirement regardless of package density. Critical applications such as medical devices and high-reliability electronics typically specify coverage toward the upper end of the target range.<\/p>\n<p>Coverage goals must appear in the test plan before layout freeze. The plan should specify the numerator, or nets verified, and the denominator, or total nets in scope, to create a measurable baseline. That baseline must identify which verification methods count toward coverage, since different methods address different net types. The plan also needs to tie these metrics to a specific board revision so the coverage report remains traceable as the design evolves. Intentionally excluded nets require written justification and a compensating test method.<\/p>\n<p><a href=\"https:\/\/proactivepcb.com\/quote\/\" target=\"_blank\" rel=\"noindex nofollow\">Request a documented ICT coverage plan<\/a> aligned to program regulatory requirements.<\/p>\n<h2>Step 2: Map the Netlist to Practical Test-Point Access<\/h2>\n<p>A netlist-to-access audit compares every electrical net against physical probe availability before placement is locked. <a href=\"https:\/\/pcbandassembly.com\/capability\/in-circuit-testing\" target=\"_blank\" rel=\"noindex nofollow\">Every net requiring ICT verification must have an accessible contact point, which becomes increasingly difficult on flip-chip and BGA-adjacent assemblies<\/a>.<\/p>\n<p>The audit classifies each net into one of four categories:<\/p>\n<ol>\n<li>Directly probeable via a dedicated test pad<\/li>\n<li>Accessible through an untented via on a breakout trace<\/li>\n<li>Reachable only through boundary scan or vectorless techniques<\/li>\n<li>Excluded with documented justification and a compensating method<\/li>\n<\/ol>\n<p>Nets in categories three and four must be identified before component placement. Reserve test access during placement by establishing keep-out zones for critical nets before placement is locked, and use test vias on inner or bottom layers where top-side space is exhausted. Any net left in category four without a compensating method represents a defect-escape risk. The next step addresses this risk by defining physical design rules that move nets into categories one or two whenever possible.<\/p>\n<h2>Step 3: Apply Concrete Test-Pad Rules for Flip-Chip Layouts<\/h2>\n<p>The physical design rules in this step ensure contact points meet dimensional and spacing requirements for reliable bed-of-nails probing. These rules support consistent ICT access on dense flip-chip and BGA layouts.<\/p>\n<figure style=\"text-align: center\"><img decoding=\"async\" src=\"https:\/\/cdn.aigrowthmarketer.co\/1785164932475-92d95a5bb500.webp\" alt=\"Macro view of dense rows of electronic components and interconnects on a board.\" style=\"max-height: 500px\" loading=\"lazy\"><figcaption><em>Advanced interconnect and high-density assembly beyond standard PCBA \u2014 wire bonding, flip chip, and hybrid HDI builds engineered for compact, mission-critical performance.<\/em><\/figcaption><\/figure>\n<p>The following pad and spacing parameters represent industry-documented minimums for reliable bed-of-nails contact:<\/p>\n<ul>\n<li><strong>Pad diameter:<\/strong> Test pads of 0.9\u20131.0 mm diameter are commonly recommended for reliable ICT spring-probe contact, with a minimum of 0.6 mm acceptable per probe manufacturers.<\/li>\n<li><strong>Center-to-center spacing:<\/strong> Minimum 1.27 mm, with greater than 1.9 mm recommended as the production standard to allow standard lower cost probes.<\/li>\n<li><strong>Component clearance:<\/strong> Test point keep-out zones should be 20 mils (approximately 0.5 mm) from component edges to prevent pogo pin damage during probing.<\/li>\n<li><strong>Board-edge clearance:<\/strong> Test pads must be located a minimum of 0.0625 inches (1.59 mm) from the PCB edge, or 0.125 inches from rails.<\/li>\n<li><strong>Side placement:<\/strong> Placing all test points on the bottom solder side avoids the significant cost of dual-side ICT fixtures.<\/li>\n<li><strong>Via test points:<\/strong> Vias may serve as test points only if untented. Microvias and tented vias are unsuitable.<\/li>\n<li><strong>Surface finish:<\/strong> ENIG or chem-tin finish supports reliable probe contact.<\/li>\n<\/ul>\n<p><a href=\"https:\/\/www.acculogic.com\/hubfs\/DFT%20-%20simplified.pdf?hsLang=en\" target=\"_blank\" rel=\"noindex nofollow\">At least two, preferably three, tooling holes placed on opposite diagonal corners of the PCB<\/a> are required for reliable fixture alignment.<\/p>\n<h2>Step 4: Combine Boundary Scan and AXI for Hidden Nets<\/h2>\n<p>A boundary-scan ICT hybrid strategy maintains coverage on nets that lack direct probe access. Modern ICT platforms integrate boundary scan, or JTAG\/IEEE 1149.1, directly into the test program and enable hybrid strategies that reach coverage levels not possible with either method alone.<\/p>\n<p>The decision tree below guides method selection based on net type and physical access:<\/p>\n<table>\n<thead>\n<tr>\n<th>Net Condition<\/th>\n<th>Recommended Method<\/th>\n<th>Coverage Contribution<\/th>\n<th>Limitation<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>Accessible test pad present<\/td>\n<td>ICT bed-of-nails<\/td>\n<td>Direct nodal coverage<\/td>\n<td>Requires DFT-compliant pad<\/td>\n<\/tr>\n<tr>\n<td>Digital net under BGA no probe access<\/td>\n<td>Boundary scan (IEEE 1149.1)<\/td>\n<td>Interconnect continuity on scan-compliant devices<\/td>\n<td>Analog components not covered<\/td>\n<\/tr>\n<tr>\n<td>Hidden solder joint under BGA CSP or shield<\/td>\n<td>AXI (Automated X-Ray Inspection)<\/td>\n<td>Joint geometry and voiding<\/td>\n<td>Does not verify electrical function<\/td>\n<\/tr>\n<tr>\n<td>High-pin-count BGA no full probe access<\/td>\n<td>Vectorless test (VTEP\/TestJet)<\/td>\n<td>Open-joint detection via capacitance measurement<\/td>\n<td>Probabilistic not deterministic<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>Engineering teams benefit from coverage reports that list nets covered by boundary scan, ICT, flying probe, X-ray, AOI and FCT plus explicitly excluded nets with reasons. That view clarifies remaining test needs.<\/p>\n<p>JTAG Technologies Board DFT Guidelines recommend quantifying boundary-scan testability before layout freeze, estimating coverage percentage, identifying gaps and prioritizing small design changes that improve results.<\/p>\n<p><a href=\"https:\/\/proactivepcb.com\/quote\/\" target=\"_blank\" rel=\"noindex nofollow\">Request a boundary-scan ICT hybrid strategy<\/a> tailored to an FC PCBA.<\/p>\n<h2>Step 5: Use a 12-Metric ICT Coverage Report Template<\/h2>\n<p>A defensible ICT coverage report separates results by method and explicitly states the numerator, denominator, included methods and board revision. This structure prevents a single undefined percentage from masking gaps in coverage.<\/p>\n<p>The 12-metric template below provides a ready-to-use structure for supplier deliverables and SOW attachments:<\/p>\n<table>\n<thead>\n<tr>\n<th>Metric<\/th>\n<th>Definition<\/th>\n<th>Acceptable Threshold<\/th>\n<th>Reporting Field<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>Total nets in scope<\/td>\n<td>All electrical nets in the netlist for the stated board revision<\/td>\n<td>Denominator for all coverage calculations<\/td>\n<td>Integer count revision label<\/td>\n<\/tr>\n<tr>\n<td>Directly probed nets<\/td>\n<td>Nets with a physical test pad contacted by a bed-of-nails or flying probe<\/td>\n<td>Maximize; document all<\/td>\n<td>Integer count % of total<\/td>\n<\/tr>\n<tr>\n<td>Boundary-scan covered nets<\/td>\n<td>Nets verified via IEEE 1149.1 scan chain<\/td>\n<td>Document all scan-compliant devices and chain order<\/td>\n<td>Integer count BSDL file version<\/td>\n<\/tr>\n<tr>\n<td>Vectorless-tested pins<\/td>\n<td>Pins verified by VTEP or TestJet capacitance measurement<\/td>\n<td>Document detection probability per device<\/td>\n<td>Integer count method identifier<\/td>\n<\/tr>\n<tr>\n<td>AXI-inspected joints<\/td>\n<td>Solder joints verified by automated X-ray<\/td>\n<td>All hidden BGA\/CSP joints<\/td>\n<td>Joint count pass\/fail criteria<\/td>\n<\/tr>\n<tr>\n<td>Open-circuit test coverage<\/td>\n<td>Percentage of nets tested for open-circuit conditions<\/td>\n<td>High overall; prioritize critical nets<\/td>\n<td>Percentage<\/td>\n<\/tr>\n<tr>\n<td>Short-circuit test coverage<\/td>\n<td>Percentage of net pairs tested for short conditions<\/td>\n<td>High overall<\/td>\n<td>Percentage<\/td>\n<\/tr>\n<tr>\n<td>Component value verification<\/td>\n<td>Passives and active devices verified for value or orientation<\/td>\n<td>All accessible components<\/td>\n<td>Count and % of BOM<\/td>\n<\/tr>\n<tr>\n<td>Intentionally excluded nets<\/td>\n<td>Nets removed from coverage scope with written justification<\/td>\n<td>Each exclusion requires compensating method<\/td>\n<td>Net list justification text compensating method<\/td>\n<\/tr>\n<tr>\n<td>Overall structural coverage<\/td>\n<td>Combined percentage across all methods above<\/td>\n<td>High minimum; elevated for medical or safety-critical designs<\/td>\n<td>Percentage method breakdown<\/td>\n<\/tr>\n<tr>\n<td>Board revision<\/td>\n<td>Schematic and layout revision to which the report applies<\/td>\n<td>Must match production traveler<\/td>\n<td>Revision identifier date<\/td>\n<\/tr>\n<tr>\n<td>Test program version<\/td>\n<td>Software version of the ICT program used<\/td>\n<td>Must be under configuration control<\/td>\n<td>Version string release date<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h2>Step 6: Write Supplier ICT Coverage Acceptance Clauses<\/h2>\n<p>Supplier agreements for regulated programs need contractual language that ties ICT coverage to acceptance criteria. The checklist below provides clause-ready language for RFQs and SOWs.<\/p>\n<table>\n<thead>\n<tr>\n<th>Clause Topic<\/th>\n<th>Required Language Summary<\/th>\n<th>Acceptance Criterion<\/th>\n<th>Verification Method<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>Minimum coverage target<\/td>\n<td>Supplier shall achieve and document overall structural ICT coverage at or above the program-specified threshold prior to first article acceptance<\/td>\n<td>Per program requirement; high coverage for safety-critical nets<\/td>\n<td>Signed coverage report board revision matched<\/td>\n<\/tr>\n<tr>\n<td>Critical-net 100% rule<\/td>\n<td>All nets designated as critical in the test plan shall achieve 100% structural verification by ICT, boundary scan or documented compensating method<\/td>\n<td>Zero unverified critical nets<\/td>\n<td>Net-by-net coverage table in report<\/td>\n<\/tr>\n<tr>\n<td>Exclusion justification<\/td>\n<td>Any net excluded from structural coverage shall be listed by name with written technical justification and an identified compensating test method<\/td>\n<td>No undocumented exclusions<\/td>\n<td>Exclusion register in coverage report<\/td>\n<\/tr>\n<tr>\n<td>Boundary-scan documentation<\/td>\n<td>Supplier shall provide BSDL file versions, chain order and tested or excluded net lists tied to the board revision used for production<\/td>\n<td>Files delivered with first article package<\/td>\n<td>BSDL version audit against production traveler<\/td>\n<\/tr>\n<tr>\n<td>Report format and revision control<\/td>\n<td>Coverage report shall state numerator, denominator, methods, board revision and test program version. Report shall be updated for each engineering change order affecting test access.<\/td>\n<td>Report revision matches production revision<\/td>\n<td>Configuration management audit<\/td>\n<\/tr>\n<tr>\n<td>Fixture calibration traceability<\/td>\n<td>Supplier shall maintain documented fixture calibration and maintenance records available for customer audit<\/td>\n<td>Records current per maintenance schedule<\/td>\n<td>Maintenance log review<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h2>Step 7: Maintain ICT Fixtures and Calibration Schedules<\/h2>\n<p>ICT fixture condition directly affects coverage validity. A fixture with worn or contaminated probes produces false failures and missed defects, which undermines the coverage percentage stated in the report. Standard-duty pogo pins last through a defined cycle range, while high-grade pins reach higher cycle counts. These ratings guide fixture service intervals and spares inventory.<\/p>\n<p>The recommended maintenance schedule for regulated production environments is:<\/p>\n<ul>\n<li><strong>Daily:<\/strong> Visual inspection of pogo pin tips for damage or contamination plus isopropyl alcohol wipe to remove flux residue.<\/li>\n<li><strong>Weekly:<\/strong> Pull-test verification on a known-good board with rejection of any pin showing contact-resistance variance beyond baseline.<\/li>\n<li><strong>Monthly:<\/strong> Verification of probe travel distance and alignment registration.<\/li>\n<li><strong>Quarterly:<\/strong> Full fixture calibration with harness continuity checks and documented alignment updates that supply the traceable maintenance records required by regulated production lines.<\/li>\n<li><strong>At cycle-life threshold:<\/strong> Comprehensive probe-plate inspection and probe replacement at the rated cycle threshold.<\/li>\n<\/ul>\n<p>Preventative maintenance programs for ICT fixtures use scheduled inspections based on predefined calendar dates or fixture cycle times to prevent downtime and maintain measurement accuracy. All maintenance activities should be captured in a written log available for customer and quality audits.<\/p>\n<p>High-mix or revision-prone designs benefit from a hybrid strategy that uses flying probe for NPI and early ramp, then transitions to dedicated bed-of-nails fixtures once the design is frozen and volume justifies the investment.<\/p>\n<h2>Common FC PCBA ICT Challenges and Fixes<\/h2>\n<p><strong>Incomplete net access.<\/strong> The most frequent cause of coverage shortfalls on FC PCBAs is the absence of dedicated test pads on breakout traces. Adding test points after fabrication requires remanufacturing the board. A netlist-to-access audit completed before placement lock with test pad requirements written into the DFT checklist mitigates this risk.<\/p>\n<p><strong>Ambiguous exclusion justification.<\/strong> Coverage reports that list excluded nets without a compensating method or written technical rationale do not satisfy regulated-program documentation requirements. Any intentionally untested node must be documented in the test plan with a compensating method such as boundary scan or functional test rather than left as an omission by oversight. Each exclusion entry in the coverage report should name the net, state the access constraint, identify the compensating method and carry an engineer signature.<\/p>\n<p><strong>Fixture drift and false failures.<\/strong> Probe wear, flux contamination and alignment shift cause contact-resistance increases that produce false failures and reduce effective coverage. For PCBs containing large BGAs or small MLCCs near board center, a strain-gauge survey during fixture development is recommended. Measured strain that exceeds program thresholds requires additional support pins to prevent warpage-induced component fractures that can pass ICT yet cause field failures. Fixture drift is controlled through the weekly known-good-board verification and quarterly calibration described in Step 7.<\/p>\n<h2>Frequently Asked Questions<\/h2>\n<h3>What ICT coverage percentage should a defense or aerospace FC PCBA target?<\/h3>\n<p>The accepted range for high-reliability programs emphasizes high overall structural coverage with critical nets such as power, clock, reset and safety-critical signals requiring 100% verification by ICT, boundary scan or a documented compensating method. Medical device programs and safety-critical applications typically require coverage toward the upper end of the target range. The specific target should appear in the test plan and the supplier SOW before layout freeze so that DFT decisions during design directly support the contractual requirement.<\/p>\n<figure style=\"text-align: center\"><img decoding=\"async\" src=\"https:\/\/cdn.aigrowthmarketer.co\/1785164949205-3a21268eaee0.webp\" alt=\"A military armored vehicle with a mounted electro-optical sensor system.\" style=\"max-height: 500px\" loading=\"lazy\"><figcaption><em>ITAR-registered manufacturing for aerospace and defense. Ruggedized, traceable, high-reliability assemblies \u2014 certified to Navy and Army specifications \u2014 built for durability and program longevity.<\/em><\/figcaption><\/figure>\n<h3>How does boundary scan complement ICT on flip-chip PCBAs?<\/h3>\n<p>Flip-chip and BGA packages make solder balls physically inaccessible after assembly. Boundary scan, or IEEE 1149.1 or JTAG, uses on-chip test logic to verify interconnect continuity on digital nets without requiring a physical probe at each ball. ICT handles accessible discrete and passive components, while boundary scan confirms continuity on digital IC interconnects. The two methods together cover nets that neither can address alone. Boundary scan does not cover analog components or nets connected only to non-scan-compliant devices, so those nets require ICT test pads, vectorless techniques or AXI.<\/p>\n<h3>What belongs in a compliant ICT coverage report for a regulated program?<\/h3>\n<p>A compliant report states the total nets in scope, the count and percentage verified by each method such as direct probe, boundary scan, vectorless and AXI, the list of intentionally excluded nets with written technical justification and compensating methods, the board revision and the test program version. A single combined percentage does not satisfy regulated programs. The report must be updated for every engineering change order that affects test access and must be traceable to the production traveler for the same revision.<\/p>\n<h3>When does a program justify a dedicated bed-of-nails ICT fixture versus flying probe?<\/h3>\n<p>Bed-of-nails ICT fixtures deliver faster test cycle times and are economically favorable for stable higher volume designs where the fixture cost amortizes across many boards. Flying probe testing requires no custom tooling, which makes it a practical choice for prototypes, low-volume builds and designs still undergoing engineering changes, since a layout change that moves a test pad can require fixture rework or rebuilding. A common approach for regulated programs uses flying probe during NPI and early ramp, then transitions to a dedicated fixture once the design is frozen and volume justifies the investment.<\/p>\n<h3>How does Pro-Active Engineering support ICT coverage documentation for regulated programs?<\/h3>\n<p>Pro-Active Engineering integrates test fixture design, ICT program development, boundary-scan strategy and coverage reporting into a single engineering workflow. The team performs netlist-to-access audits during the design phase, applies DFT rules before layout freeze, builds and maintains bed-of-nails fixtures and delivers coverage reports that meet the 12-metric structure described above. All documentation is produced under Pro-Active accredited quality management system, which provides the traceability required by defense, aerospace and medical OEM programs.<\/p>\n<h2>Conclusion<\/h2>\n<p>High ICT coverage on FC PCBAs relies on seven integrated steps. These steps include defining documented coverage goals, auditing netlist-to-access feasibility, applying DFT-compliant pad rules, deploying a boundary-scan and AXI hybrid strategy, building a 12-metric coverage report, embedding supplier acceptance clauses in SOWs and maintaining fixtures on a calibrated schedule. Each step depends on decisions made before layout freeze. Addressing coverage requirements after first build often results in redesigns, fixture rework and defect-escape risk on regulated programs.<\/p>\n<p>Pro-Active Engineering delivers this process as an integrated workflow from DFT review through fixture build, test execution and documented coverage reporting under one certified quality management system.<\/p>\n<p><a href=\"https:\/\/proactivepcb.com\/quote\/\" target=\"_blank\" rel=\"noindex nofollow\">Engage Pro-Active Engineering&#8217;s ICT fixture and coverage-report services<\/a> for FC PCBA programs.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Pro-Active Engineering outlines DFT rules, boundary scan and AXI methods to maximize ICT coverage on flip-chip PCBA. Get the full guide.<\/p>\n","protected":false},"author":68,"featured_media":222,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"inline_featured_image":false,"footnotes":""},"categories":[10],"tags":[],"class_list":["post-243","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-pcb-testing-validation"],"_links":{"self":[{"href":"https:\/\/proactivepcb.com\/articles\/wp-json\/wp\/v2\/posts\/243","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/proactivepcb.com\/articles\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/proactivepcb.com\/articles\/wp-json\/wp\/v2\/types\/post"}],"replies":[{"embeddable":true,"href":"https:\/\/proactivepcb.com\/articles\/wp-json\/wp\/v2\/comments?post=243"}],"version-history":[{"count":3,"href":"https:\/\/proactivepcb.com\/articles\/wp-json\/wp\/v2\/posts\/243\/revisions"}],"predecessor-version":[{"id":1438,"href":"https:\/\/proactivepcb.com\/articles\/wp-json\/wp\/v2\/posts\/243\/revisions\/1438"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/proactivepcb.com\/articles\/wp-json\/wp\/v2\/media\/222"}],"wp:attachment":[{"href":"https:\/\/proactivepcb.com\/articles\/wp-json\/wp\/v2\/media?parent=243"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/proactivepcb.com\/articles\/wp-json\/wp\/v2\/categories?post=243"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/proactivepcb.com\/articles\/wp-json\/wp\/v2\/tags?post=243"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}